wafer.space Community

Test of writing to the lower 4 bits of 64 words at 25MHz (also works at 50MHz but it's at the sampling limit of the USB scope).

12:52 a.m.

Test setup with one Digilent Analog Discovery 2.

6

Tim Edwards

Thanks to everyone who helped me get my SRAM chips tested! The COB boards work great (enough of them, anyway), the breakout board works great, and I was able to confirm read and write operation of all three of the 3.3V SRAM macros (256, 512, and 1024 byte) up to 50MHz. More extensive and exhaustive testing will be done, but getting a quick answer as to whether the 3.3V SRAMs are viable for the next tapeout was key.

Can we get some amount of reporting as to how good as a PUF that SRAM behaves? Like, reading the power-on bit pattern of a few dies and seeing how stable and unique it is per-die? If it's at least not-terrible, I could try next week about getting a probably-smallest-tested SRAM macro set up, if I can think of a way to read it at all without an electrical pad contact to the die.

@namibj : I don't have any kind of temperature force unit, so I won't be able to determine if the power-up pattern is stable over temperature. I would tend to expect it to be dependent on the 3.3V supply ramp, as well.

Tim Edwards

@namibj : I don't have any kind of temperature force unit, so I won't be able to determine if the power-up pattern is stable over temperature. I would tend to expect it to be dependent on the 3.3V supply ramp, as well.

temperature stability shouldn't matter tooo much; trying voltage corners of the nominal-3v3, or, if not difficult, operation at reduced voltage (e.g. the foundry Dualgate SCL is rated down to 1.62V) would be plenty sufficcient to get an idea of if it's looking to be usable or not. It doesn't have to be an exact match of the pattern, it just has to be closest-match by a physically-inspired metric (notably, I'd figure accounting for the impact of mismatch in the sense amplifiers would help the statistical-model-based matching, like perhaps using a polynomial chaos expansion surrogate model to decorrelate w.r.t. supply ramps and (as needed) temperature, and focus on die-specific mismatch instead. It'd be a next-week thing though, as this week I got the extended ttgf0p3 and have already pushed schedule from the next two days to the weekend.

namibj

Can we get some amount of reporting as to how good as a PUF that SRAM behaves? Like, reading the power-on bit pattern of a few dies and seeing how stable and unique it is per-die? If it's at least not-terrible, I could try next week about getting a probably-smallest-tested SRAM macro set up, if I can think of a way to read it at all without an electrical pad contact to the die.

I think what you will find is that some bit will always be the same at power-on but some will likely be more random. This means you'll need to transform this power-up pattern with random bits into a reproducible one.

Chips4Makers aka Staf Verhaegen

I think what you will find is that some bit will always be the same at power-on but some will likely be more random. This means you'll need to transform this power-up pattern with random bits into a reproducible one.

Well, I mostly care about it as being able to record them at the die sorter while the process still knows what reticle and what wafer any particular die came from (location within a reticle is obviously trivial to encode using mask ROM techniques), to then later post-packaging being able to read it out from in the circuit during e-testing and match it against the recorded database to recognize which of the dies it (with high likelihood) was, followed by printing the information onto a label or writing them into some type/choice of PROM, be it on-die or just on-PCB.

namibj

Well, I mostly care about it as being able to record them at the die sorter while the process still knows what reticle and what wafer any particular die came from (location within a reticle is obviously trivial to encode using mask ROM techniques), to then later post-packaging being able to read it out from in the circuit during e-testing and match it against the recorded database to recognize which of the dies it (with high likelihood) was, followed by printing the information onto a label or writing them into some type/choice of PROM, be it on-die or just on-PCB.

The future CoB boards will have unqiue IDs. @Andrew Wingate is hoping to keep track of the die (where from the wafer they came from) as they are loaded into the tape. I'm also looking to source a large number of I2C EEPROMs which end up being 1-2 cents each.

1

Clearly, the perfect solution is

Tim 'mithro' Ansell

The future CoB boards will have unqiue IDs. @Andrew Wingate is hoping to keep track of the die (where from the wafer they came from) as they are loaded into the tape. I'm also looking to source a large number of I2C EEPROMs which end up being 1-2 cents each.

Oh great.

First draft of 0p5x1 CoB. Revisions compared with previous CoBs / previous attempt at this one:

Principle of least surprise: Schematic has pin 1 where the project template does. Pads (except for power) are in the same order on the mezzanine connector as on the die.
Wafer space logo moved to bottom right, so it matches the top left position on the run 2 dies
Solder mask added between the die and pad ring
No Ground flood fill exclusion between die and pad ring
Pin 1 marker is in copper Feedback welcome

7:49 p.m.

One note: It'll be natural to hold these the other way up, to match the die orientation. I think that's good, but it does mean mezzanine connector pin 1 is at the bottom, which is potentially confusing. (Although at least on my motherboard, and I saw on the KianV one too, the CoB is mounted upside down anyway). And one question: The ground plated through holes between the die and the pad ring, sohuld they just be normal vias? Then all the holes should be tented, which may avoid issues with bubbles?

7:50 p.m.

Project is here: https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/0p5x1-mezzanine/run-1/0p5x1-cob (edited)

1

RebelMike

One note: It'll be natural to hold these the other way up, to match the die orientation. I think that's good, but it does mean mezzanine connector pin 1 is at the bottom, which is potentially confusing. (Although at least on my motherboard, and I saw on the KianV one too, the CoB is mounted upside down anyway). And one question: The ground plated through holes between the die and the pad ring, sohuld they just be normal vias? Then all the holes should be tented, which may avoid issues with bubbles?

IIUC/IIRC what you don't want is non-through-holes that hold an air bubble at their bottom, which get filled with epoxy that has a hard time displacing the air, thus causing those very bubbles to get stuck in the epoxy. I'm not sure if you're allowed through holes which would let the air escape down as the epoxy flows into the hole, as the epoxy could theoretically droop down and form drops on the bottom.

Cool, so probably nothing inherently wrong with keeping them, unless that's been a problem in the existing CoBs.

RebelMike

Cool, so probably nothing inherently wrong with keeping them, unless that's been a problem in the existing CoBs.

IIRC the issue before was that the bottom of those was tented, but the top was open. The cob bond house might have issues with open holes if there's worry about epoxy dripping and leaving hardened residues in places they shouldn't be; I don't know the viscosity and surface tension enough to judge if that's an actual risk with the current chemistry and thicknesses, though. IMO keep them open and prepare to be told to tent the tops if necessary; I won't have time to search for what judgement the earlier discussions came up with, until 2 weeks from now.

And the 0p5x0p5 version:

7

Is there a convention for the pin numbering of the wafer.space standard template padring pads? For instance, it looks like the left end of the south side is always clk by default, so is this a good one to call pin 1, and the rest increment in an anti-clockwise direction from there?

Yes. The intention is that left end of south is pin 1 in the project template, and you go anti-clockwise from there. Unfortunately the run 1 CoBs mount the die rotated by 180 degrees, so that then ends up with pin 1 at the top right.

1

RebelMike

And the 0p5x0p5 version:

the corner pads look so cool

I did ensure my layout’s padring was compatible with the standard COB this time, but I still need to check if the COB breaks out the pins how I need them.

Tholin

I did ensure my layout’s padring was compatible with the standard COB this time, but I still need to check if the COB breaks out the pins how I need them.

As long as you have power and ground in the same place as the template it should work.

1

I’m using the level-shifting pads

6:47 p.m.

And do have different core and IO voltages in mind

The power pins are all independent on the breakout, each with their own cap. Only ground are connected together

What about IO? I've used every single pad.

Tholin

What about IO? I've used every single pad.

They are all good as well. The only pads that never make it directly to the mezzanine are the ground pads, and those are all bridged. Like Mike said, all the power pins are isolated, but also by default, have 1uF caps